Summary This paper proposes a dynamic packet buffer management algorithm for a protocol processor in a network terminal. The protocol processor is to handle high-speed data streams, more than 10 Gb/s, in a network interface card (NIC). There are two types of packet buffer management algorithms, static and dynamic. In general, the dynamic buffer management algorithms work better than the static ones for reducing the packet loss ratio. However, conventional dynamic buffer management algorithms do not utilize packet buffer memory efficiently. Therefore, we propose an algorithm, which contributes to fairness and full utilization of the packet buffer memory. Our experimental results show that the proposed algorithm improves the packet loss ratio...
While traffic volume of real-time applications is rapidly increasing, current routers do not guarant...
The following buffer management problem arises in network switches providing differentiated services...
This paper explores the hardware and software mechanisms necessary for an efficient programmable 10 ...
A Buffer management algorithm plays an important role in determining the packet loss ratio in a comp...
A Network Interface Card (NIC) is used for receiving the packets, processing the packets, passing th...
A packet buffer for a protocol processor is a large shared memory space that holds incoming data pac...
A packet buffer for the protocol processor is a large memory space that holds incoming data packets ...
In a wide area network that uses store-and-forward technology, a packet switch buffers incoming data...
One of the main problems concerning high-performance communications networks is the unavoidable cong...
Performance of ATM networks depends on switch performance and architecture. This paper presents a si...
Earlier studies have exploited statistical multiplexing of flows in the core of the Internet to redu...
High-speed routers rely on well-designed packet buffers that support multiple queuing, large capacit...
ABSTRACT: All packet switches contain packet buffers to hold packets during times of congestion. Hig...
Keeping the delay experienced by packets while travelling from a source to a destination below certa...
Switch and router architectures employing a shared buffer are known to provide high throughput, low ...
While traffic volume of real-time applications is rapidly increasing, current routers do not guarant...
The following buffer management problem arises in network switches providing differentiated services...
This paper explores the hardware and software mechanisms necessary for an efficient programmable 10 ...
A Buffer management algorithm plays an important role in determining the packet loss ratio in a comp...
A Network Interface Card (NIC) is used for receiving the packets, processing the packets, passing th...
A packet buffer for a protocol processor is a large shared memory space that holds incoming data pac...
A packet buffer for the protocol processor is a large memory space that holds incoming data packets ...
In a wide area network that uses store-and-forward technology, a packet switch buffers incoming data...
One of the main problems concerning high-performance communications networks is the unavoidable cong...
Performance of ATM networks depends on switch performance and architecture. This paper presents a si...
Earlier studies have exploited statistical multiplexing of flows in the core of the Internet to redu...
High-speed routers rely on well-designed packet buffers that support multiple queuing, large capacit...
ABSTRACT: All packet switches contain packet buffers to hold packets during times of congestion. Hig...
Keeping the delay experienced by packets while travelling from a source to a destination below certa...
Switch and router architectures employing a shared buffer are known to provide high throughput, low ...
While traffic volume of real-time applications is rapidly increasing, current routers do not guarant...
The following buffer management problem arises in network switches providing differentiated services...
This paper explores the hardware and software mechanisms necessary for an efficient programmable 10 ...